Testable and self-repairable structured logic design

TitleTestable and self-repairable structured logic design
Publication TypeConference Paper
Year of Publication2006
AuthorsAlsaiari, U., and R. Saleh
Conference NameCircuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Pagination4 pp.
Keywordsapplication specific integrated circuits, ASIC, built-in self test, CAD tool design, circuit CAD, deep submicron technology, design for testability, FPGA, integrated circuit testing, logic circuits, logic design, PLA, programmability features, programmable logic arrays, ROM, structured arrays, testability
Abstract

Deep submicron technology is forcing designers away from traditional ASIC design styles toward structured arrays for the implementation of logic circuits. Structured arrays have many inherent benefits in terms of CAD tool design, testability and reliable fabrication. FPGAs and structured ASIC fabrics are two examples, but their speed, area and power overheads are high due to their programmability features. If programmability is removed, it is possible to reduce the overhead. Perhaps it is time to revisit the use of structured logic for fixed-function blocks, such as ROMs and PLAs, to determine if they are better-suited for this purpose. In particular, this paper investigates the PLA from the self-test and self-repair perspectives. ASIC blocks are known to have limitations in terms of self-test, but have little or no hope of providing self-repair. In contrast, this paper proposes straight-forward solutions for self-test and self-repair of PLAs. We find that it can provide 100% self-test coverage, and a very high probability of self-repair at the cost of area overhead

URLhttp://dx.doi.org/10.1109/ISCAS.2006.1693910
DOI10.1109/ISCAS.2006.1693910

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