Energy Recovery from High-Frequency Clocks Using DC-DC Converters

TitleEnergy Recovery from High-Frequency Clocks Using DC-DC Converters
Publication TypeConference Paper
Year of Publication2008
AuthorsAlimadadi, M., S. Sheikhaei, G. Lemieux, S. Mirabbasi, W. G. Dunford, and P. Palmer
Conference NameSymposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
Pagination162 -167
Date Publishedapr.
Keywordsclock duty cycle, clocks, DC-DC power convertors, digital integrated circuits, driver circuits, energy recovery, high frequency clocks, large digital chips, multi GHz clock, on-chip DC-DC converters, single-edge-triggered flops, tapered buffer chain
Abstract

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages.

URLhttp://dx.doi.org/10.1109/ISVLSI.2008.102
DOI10.1109/ISVLSI.2008.102

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