A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm

TitleA "soft++" eFPGA physical design approach with case studies in 180nm and 90nm
Publication TypeConference Paper
Year of Publication2006
AuthorsAken'Ova, V., and R. Saleh
Conference NameEmerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Pagination6 pp.
Date Publishedmar.
Keywords180 nm, 90 nm, ASIC digital flow, clock tree synthesis, CMOS logic circuits, CMOS technology, embedded FPGA, embedded systems, field programmable gate arrays, floorplanning, generic standard cells, integrated circuit layout, interconnect-planning, logic design, programmable fabrics, RTL level, soft++ eFPGA

Our recent work in embedded FPGAs has been focused on a soft IP approach where programmable fabrics are described at the RTL level and implemented using the ASIC digital flow and generic standard cells. Early results showed significant penalties in area, delay, and power overhead. However, using tactical standard cells and a structured physical design approach within such a flow, we were able to obtain large savings in area and delay. We defined this new approach as soft++ eFPGA. This paper provides details of the physical design flow, with particular emphasis on floor-planning, interconnect-planning, and clock tree synthesis. The advantages of our approach in handling larger circuits are demonstrated on a set of realistic benchmark circuits implemented in 180nm and 90nm CMOS process technology


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