Real-time systolic array processor for 2-D spatial filtering

TitleReal-time systolic array processor for 2-D spatial filtering
Publication TypeJournal Article
Year of Publication1988
AuthorsAboulnasr, T., and W. Steenaart
JournalCircuits and Systems, IEEE Transactions on
Pagination451 -455
Date Publishedapr.
Keywords262144 pixel, 2D digital filters, 512 pixel, cellular arrays, computerised picture processing, finite-length registers, local state-space filters, microprocessor chips, modular structure, multiplier/adder cells, real-time image processing, real-time systems, ROM/adder cells, signal processing equipment, spatial filtering, state-space methods, systolic array processor, two-dimensional digital filters, VLSI, VLSI implementation

The use of systolic arrays (SA) to implement two-D local state-space (LSS) digital filters for real-time image processing is presented. The simple modular structure of the SA is ideal for VLSI implementation. The array used is composed of ROM/adder (or multiplier/adder) cells and is shown to be 100% efficient. The size of the array is equal to the overall size of the system matrix and is much smaller than arrays where the number of cells equals the number of image pixels. Still, this array is capable of processing a 512 times;512 image in less than 1/30 seconds allowed in real-time applications for second-order filters. The use of ROMs along with the inherent good performance of LSS filters under the effect of finite-length registers, makes this implementation desirable. The array is also far less expensive than other proposed real-time two-D digital filter implementations


a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia