Tor Aamodt is an Associate Professor in the Department of Electrical and Computer Engineering at the University of British Columbia. He received his BASc (in Engineering Science), MASc and PhD at the University of Toronto. His current research focuses on architecture and microarchitecture of manycore accelerators such as graphics processing units (GPUs), heterogeneous multicore processors, and analytical performance modeling of modern processor architectures. He has published over 20 papers in top computer architecture conferences and journals and has five patents related to computer architecture. Recent work on implementing hardware transactional memory on GPUs, performed by his research group at UBC, was selected as a "Top Pick" from computer architecture conferences by IEEE Micro magazine. He has served on the technical program committee for several international computer architecture conferences. As a graduate student, he spent about a year as an intern in Intel's Microarchitecture Research Lab. Prior to joining UBC he worked at NVIDIA on the GeForce 8 Series GPU (G80).
| EECE 353 |
Digital Systems Design Advanced combinational and sequential electronic system design. Hardware specification, modeling, and simulation using hardware description languages (HDLs) and CAD tools. Design with programmable logic including FPGA's. Applications include complex state machines, microcontrollers, arithmetic circuits, and interface units. Credit can be given for only one of EECE 353 or EECE 379. |
| EECE 476 |
Computer Architecture Quantitative principles, instruction set design, methods for performance improvements, pipelining, multiple instruction issue, dynamic scheduling, branch prediction, memory systems, caches, multi-core, multiple views of the design space, other advanced architectures. Credit will be given for only one of CPSC 313 or EECE 476. |
| EECE 527 |
Advanced Computer Architecture Modern processor design with an emphasis on superscalar microarchitecture. Topics include: Quantitative principles, pipelining, memory hierarchy, multithreading, advanced instruction flow, and data flow techniques. Course Outline The microprocessor industry is undergoing a dramatic change with the widespread introduction of multicore processors. This course is about the numerous ways chip architects translate an ever growing supply of transistors into exciting products that take advantage of process technology improvements. |
| 2010 |
Visualizing complex dynamics in many-core accelerator architectures Conference Paper | Performance Analysis of Systems Software (ISPASS), 2010 IEEE International Symposium on |
| 2010 |
Accelerating trace computation in post-silicon debug Conference Paper | Quality Electronic Design (ISQED), 2010 11th International Symposium on |
| 2009 |
Dynamic Warp Formation: Efficient MIMD Control Flow on SIMD Graphics Hardware Journal Article | ACM Transactions on Architecture and Code Optimization |
| 2009 |
Complexity effective memory access scheduling for many-core accelerator architectures Conference Paper | Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on |
| 2009 |
Architecting graphics processors for non-graphics compute acceleration Conference Paper | Communications, Computers and Signal Processing, 2009. PacRim 2009. IEEE Pacific Rim Conference on |
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