Faculty
Professor
Tor Aamodt
Tor Aamodt is a Professor in the Department of Electrical and Computer Engineering at the University of British Columbia where he has been a faculty member since 2006. His current research focuses on the architecture of general purpose GPUs and energy efficient computing. Three of his papers related to the architecture of general purpose GPUs have been selected as "Top Picks" by IEEE Micro Magazine and one as a "Research Highlight" by Communications of the ACM magazine. He is in the MICRO Conference Hall of Fame. He was an Associate Editor for IEEE Computer Architecture Letters from 2012 to 2015 and the International Journal of High Performance Computing Applications, was Program Chair for ISPASS 2013, General Chair for ISPASS 2014, and has served on numerous conference technical program committees. He was a Visiting Associate Professor in the Computer Science Department at Stanford University during his 2012-2013 sabbatical. He was awarded an NVIDIA Academic Partnership Award in 2010, a NSERC Discovery Accelerator for 2016-2019 and a 2016 Google Faculty Research Award (the first at UBC since 2012). From late 2004 to early 2006 he worked at NVIDIA on the memory system architecture ("framebuffer") of the GeForce 8 Series GPU -- the first NVIDIA GPU to support CUDA. He received his BASc (in Engineering Science), MASc and PhD at the University of Toronto.
He is a Professional Engineer in the province of British Columbia (registered with APEGBC).
SELECTED PUBLICATIONS (Google Scholar Profile)
Cache-Conscious Wavefront Scheduling (CACM Research Highlight)
Hardware Transactional Memory for GPU Architectures (IEEE Micro Top Picks)
Cache Coherence for GPU Architectures (IEEE Micro Top Picks)
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
Research Areas
Research Groups
Courses
| CPEN 411 |
Computer Architecture Quantitative principles, instruction set design, methods for performance improvements, pipelining, multiple instruction issue, dynamic scheduling, branch prediction, memory systems, caches, multi-core, multiple views of the design space, other advanced architectures. Credit will be given for only one of CPSC 313 or CPEN 411. [3-0-2] |
| CPEN 511 |
Advanced Computer Architecture Modern processor design with an emphasis on superscalar microarchitecture. Topics include: Quantitative principles, pipelining, memory hierarchy, multithreading, advanced instruction flow, and data flow techniques. Course Outline The microprocessor industry is undergoing a dramatic change with the widespread introduction of multicore processors. This course is about the numerous ways chip architects translate an ever growing supply of transistors into exciting products that take advantage of process technology improvements. |
| CPEN 311 |
Digital Systems Design Advanced combinational and sequential electronic system design. Hardware specification, modeling, and simulation using hardware description languages (HDLs) and CAD tools. Design with programmable logic including FPGA's. Applications include complex state machines, microcontrollers, arithmetic circuits, and interface units. Credit can be given for only one of CPEN 311 or EECE 379. [3-3-0] |
| CPEN 211 |
Introduction to Microcomputers Boolean algebra; combinational and sequential circuits; organization and operation of microcomputers, memory addressing modes, representation of information, instruction sets, machine and assembly language programming, systems programs, I/O structures, I/O interfacing and I/O programming, introduction to digital system design using microcomputers. [4-2-2*] Course Overview This course is a combination of two previous courses - EECE 256 and EECE 259 |
| CPEN 391 |
Computer Systems Design Studio II Design and implementation of a hardware platform and software design and implementation at the operating system and application layers. Project management skills. Effective prsentations. [2-6-0] PREREQUISITES CPEN 311 - Digital System Design |
| EECE 571T |
Compute Accelerator Architectures Summary With the approaching end of Moore's Law computer systems developers are being confronted with the challenge of increasing computing performance without using faster and more plentiful transistors. This course explores the leading approach to tackling this problem that has emerged in both industry and academic research: The use of computation accelerator architectures. |
Latest Publications
| 2016 |
Reuse distance-based probabilistic cache replacement Journal Article | ACM Transactions on Architecture and Code Optimization (TACO) |
| 2016 |
CIRCUIT-BASED APPARATUSES AND METHODS WITH PROBABILISTIC CACHE EVICTION OR REPLACEMENT Miscellaneous |
| 2016 |
Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks Conference Paper | Proceedings of the 2016 International Conference on Supercomputing |
| 2016 |
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Journal Article | arXiv preprint arXiv:1606.01607 |
| 2015 |
SLIP: reducing wire energy in the memory hierarchy Conference Paper | Proceedings of the 42nd Annual International Symposium on Computer Architecture |
| Show more |
Contact
Office: KAIS 4043The University of British Columbia
4043 - 2332 Main Mall
Vancouver BC V6T 1Z4
Canada
http://www.ece.ubc.ca/~aamodt/
