Compute Accelerator Architectures

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With the approaching end of Moore's Law computer systems developers are being confronted with the challenge of increasing computing performance without using faster and more plentiful transistors.  This course explores the leading approach to tackling this problem that has emerged in both industry and academic research:  The use of computation accelerator architectures.

This course will provide students a foundation for understanding both programmable and fixed function accelerator architectures.  The initial protion of the course will involve discussion of graphics processor units which are commonly used today for training deep neural networks.  The later portion of the course will focus on more specialized accelerators with an emphasis on machine learning accelerators.

The course will involve three programming assignments (to get familiar with using computer architecture simulators), research paper readings and presenations and a final project.


1. Course overview

2. Review of Computer Architecture

  • Instructions
  • Pipelining
  • Caches
  • Memory and memory access scheduling
  • multi core and multi threading

3. Graphics processor unit architectures

  • GPU programming model
  • GPU insturction set architecture
  • one loop approximation (multithreading and SIMT model)
  • two loop approximation (register scoreboard, operand collector)
  • three loop approximation (caches, pending memory request tables, memory controller)
  • intrudoction to the GPGPU-Sim simulator

4. Machine learning accelerators:

(a) Brief review of deep neural networks

  • Linear regression and classification
  • Single layer networks
  • Multilayer networks and back propagation
  • Convolutional neural networks
  • Survey of some recent deep networks

(b) Interface acceleration architecture

  • Approximation (bit width reduction)
  • Ineffectual computations (skipping multiplication by zero)
  • Memory organization for faster acceleration
  • Industry examples (whatever is publicly known about them)

(c) Semi-programmable ML accelerators

5. Other compute accelerators:

  • Media encoders/decoders (e.g., H264)
  • Network switches and network processors



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