@article {Viriato1992An-efficient-sy,
title = {An efficient systolic array implementation of the sign-LMS algorithm},
journal = {Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on},
volume = {39},
number = {5},
year = {1992},
month = {may.},
pages = {322 -325},
abstract = {A bit-level systolic array of the implementation of the LMS algorithm is presented. The array is divided into a 2D convolver array and a linear updater array. The structure is 100\% data flow efficient, requiring N/2 rows to implement N coefficients. The updater is made up of N/2 simple cells. The sign-LMS algorithm is used for updating the coefficients. All coefficients are updated every 2R clocks where R is the number of bits per coefficient and the clock is the bit-level clock (array clock)},
keywords = {2D convolver array, bit-level systolic array, coefficients updating, computerised signal processing, digital signal processing chips, least squares approximations, linear updater array, sign-LMS algorithm, systolic array implementation, systolic arrays},
issn = {1057-7130},
doi = {10.1109/82.142035},
url = {http://dx.doi.org/10.1109/82.142035},
author = {Viriato, L.A. and Aboulnasr, T.}
}