Recent Publications
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"SoC implementation issues for synthesizable embedded programmable logic cores",
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003, pp. 45 - 48, sep., 2003.
Abstract
"Design considerations for soft embedded programmable logic cores",
Solid-State Circuits, IEEE Journal of, vol. 40, no. 2, pp. 485 - 497, feb., 2005.
Abstract
"Programmable logic IP cores in SoC design: opportunities and challenges",
Custom Integrated Circuits, 2001, IEEE Conference on., pp. 63 -66, 2001.
Abstract
"PARALLEL EVENT-DRIVEN WAVE-FORM RELAXATION",
IEEE INTERNATIONAL CONFERENCE ON COMPUTER-DESIGN : VLSI IN COMPUTERS AND PROCESSORS: IEEE, COMP SOC; IEEE, CIRCUITS & SYST SOC, pp. 101-104, 1991.
"Improving parallel circuit simulation using high-level waveforms",
1995 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 345 E 47TH ST, NEW YORK, NY 10017, IEEE Circuits & Syst Soc, pp. 728-731, 1995.
"RECOMBINATION AT DEFECTS IN AMORPHOUS-SILICON (A-SI-H)",
Journal of Non-Crystanlline Solids, vol. 190, no. 1-2, PO BOX 211, 1000 AE AMSTERDAM, NETHERLANDS, ELSEVIER SCIENCE BV, pp. 9-20, OCT, 1995.
Abstract
"Time warping-waveform relaxation in a distributed circuit simulation environment",
38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 345 E 47TH ST, NEW YORK, NY 10017, Fed Univ Rio de Janeiro; IEEE, Circuits & Syst Soc, pp. 338-341, 1996.
"BUTENE DIMERIZATION OVER SULFATE AND TUNGSTATE MODIFIED SOLID ACIDS",
ACID-BASE CATALYSIS II, vol. 90, SARA BURGERHARTSTRAAT 25, PO BOX 211, 1000 AE AMSTERDAM, NETHERLANDS, Hokkaido Univ, Grad Sch Environm Earth Sci; Sapporo Int Commun Plaza Fdn, pp. 537-541, 1994.
Abstract
"ANION-TREATED SOLID ACIDS FOR BUTENE DIMERIZATION",
Abstracts of Paper s of the American Chemical Society, vol. 203, no. Part 2, 1155 16TH ST, NW, WASHINGTON, DC 20036, AMER CHEMICAL SOC, pp. 74-PETR, APR 5, 1992.
"FREQUENCY-DOMAIN ANALYSIS OF SWITCHED-CAPACITOR CIRCUITS CONTAINING NONIDEALITIES",
PROCEEDINGS OF THE IEEE 1993 CUSTOM INTEGRATED CIRCUITS CONFERENCE: IEEE, ELECTRON DEVICES SOC, pp. T5-&, 1993.
"SIMULATOR CHARACTERISTICS NEEDED TO INTERFACE TO ANALOG HDLS",
INTERNATIONAL CONFERENCE ON SIMULATION AND HARDWARE DESCRIPTION LANGUAGES (ICSHDL) - PROCEEDINGS OF THE 1994 WESTERN MULTICONFERENCE, PO BOX 17900, SAN DIEGO, CA 92177, SOC COMP SIMULAT, pp. 31-36, 1994.
"OPTICAL DEPHASING IN SEMICONDUCTOR MIXED-CRYSTALS",
Physical Review B, vol. 46, no. 8, ONE PHYSICS ELLIPSE, COLLEGE PK, MD 20740-3844 USA, AMERICAN PHYSICAL SOC, pp. 4564-4581, AUG 15, 1992.
Abstract
"A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers",
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, vol. 1, pp. I-173 - I-176 vol.1, may., 2003.
Abstract
"Constraint-based voltage island partitioning",
2007 IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS, 345 E 47TH ST, NEW YORK, NY 10017 USA, IEEE; Circuits & Syst Soc; RESMIQ; CMC; Hardent; ISR Technologies; Ecole Polytech Montreal, pp. 193-196, 2007.
Abstract
"Power-delay metrics revisited for 90 nm CMOS technology",
Quality of Electronic Design, 2005. ISQED 2005. 6th International Symposium on, pp. 291 - 296, mar., 2005.
Abstract
"Supply Voltage Selection in Voltage Island based SoC Design",
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 345 E 47TH ST, NEW YORK, NY 10017 USA, IEEE, pp. 219-222, 2008.
Abstract
"Generalized Power-Delay Metrics in Deep Submicron CMOS Designs",
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, no. 1, pp. 183 -189, jan., 2007.
Abstract
"Application-driven floorplan-aware voltage island design",
Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, pp. 155 -160, jun., 2008.
Abstract
"NON-RADIATIVE RECOMBINATION IN A-SIH",
AMORPHOUS SILICON TECHNOLOGY-1994, vol. 336, 9800 MCKNIGHT RD, SUITE 327, PITTSBURGH, PA 15237, MAT RES SOC, pp. 189-194, 1994.
"INFLUENCE OF DEFECTS AND TEMPERATURE ON THE LIFETIME DISTRIBUTION OF CARRIERS IN A-SI-H",
Journal of Non-Crystanlline Solids, vol. 166, no. Part 1, PO BOX 211, 1000 AE AMSTERDAM, NETHERLANDS, IUPAP; HITACHI LTD; FUJI ELECT CO LTD; INT COMMUN SPECIALISTS; BNR STL; TAYLOR & FRANCIS LTD; INST MAT; INST ELECT ENGINEERS; INT SCI FDN; WELSH DEV AGCY; SANYO ELECT CO LTD; KANEKA CORP; OXFORD INSTRUMENTS LTD; ICI ZENECA; IBM US; INST PHYS; ROYAL SOC; B, pp. 555-558, DEC, 1993.
Abstract
"THE INFLUENCE OF SPATIALLY NON-UNIFORM DENSITY-OF-STATE DISTRIBUTIONS ON THE CHARACTERISTICS OF A-SI-H THIN-FILM TRANSISTORS",
Philosophical Magazine B-Physics of Condensed Matter Statistical Mechanics Electronic Optical and Magnetic Properties, vol. 61, no. 2, ONE GUNDPOWDER SQUARE, LONDON, ENGLAND EC4A 3DE, TAYLOR & FRANCIS LTD, pp. 263-276, FEB, 1990.
"BENCHMARK CIRCUITS FOR MIXED-MODE SIMULATORS",
PROCEEDINGS OF THE IEEE 1994 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 345 E 47TH ST, NEW YORK, NY 10017, IEEE ELECTRON DEVICES SOC; IEEE SOLID STATE CIRCUITS COUNCIL, pp. 441-448, 1994.
"Structural characterization of a-Si : C : H alloys prepared by dc sputtering",
Journal of Non-Crystanlline Solids, vol. 299, no. Part B, PO BOX 211, 1000 AE AMSTERDAM, NETHERLANDS, ELSEVIER SCIENCE BV, pp. 891-895, APR 1, 2002.
Abstract
"Microstructure characterization in dc sputtered a-SiC : H films by inert gas effusion measurements",
Journal of Non-Crystanlline Solids, vol. 338, PO BOX 211, 1000 AE AMSTERDAM, NETHERLANDS, ELSEVIER SCIENCE BV, pp. 517-520, JUN 15, 2004.
Abstract
"NEW MACRO MODEL FOR ZENERS",
IEEE Circuits and Devices Magazine, vol. 9, no. 2, 345 E 47TH ST, NEW YORK, NY 10017-2394, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, pp. 7-11, MAR, 1993.
